A reduced mask process for forming a MOS gated device such as a power MOSFET uses a first mask (33) to sequentially form a cell body (50) and a source region (51) within the cell body (50), and a second mask step to form, by a silicon etch, a central opening (80,81) in the silicon surface at each cell and to subsequently undercut the oxide (60) surrounding the central opening (80,81). A contact layer (84) then fills the openings (80,81) of each cell to connect together the body (50) and source regions (51). Only one critical mask alignment step is used in the process. |