| Original document(16 pages) 中文版 |
The invention provides an integrated circuit manufacturing technique which can improve gate oxide integrity and bury a joint. In order to ensure that a hole can be etched in the thin gate oxide and the gate oxide in the burying of the joint is integrated, the best way is that another layer of a polycrystalline silicon layer without pattern is deposited above the gate oxide as soon as possible after the forming of the gate oxide. A mask for the burying of the joint is used for a secondary etching. In order to further ensure the maximum integrity of the gate oxide, the adding of a threshold voltage is completed by one layer of an oxide layer which is removed before the growth of the gate oxide and after the adding of the threshold voltage. The method can be used for the production of an N channel metal-oxide semiconductor and a complementary metal oxide semiconductor. |
Application Number
申请号 |
85107802 |
Application Date
申请日 |
1985.10.21 |
| Title 名称 |
Integrated circuit fabrication process with buried contacts |
Publication Number
公开号 |
1001907 |
Publication Date
公开日 |
1986.07.23 |
| Approval Pub. Date |
|
Granted Pub. Date |
|
| International Classification 分类号 |
H01L21/72;H01L27/04;H01L29/76 |
Applicant(s) Name
申请人 |
Texas Instruments (US) Dallas, Texas 75265, 13500 North Cental Expressway U.S.A. |
| Address 地址 |
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| Inventor(s) Name 发明人 |
Pradeep Shah |
| Attorney & Agent 代理人 |
WU SHUFANG |
| More information 更 多 信 息 |
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