Original document(5 pages)  中文版
    The present invention uses emitter-followers as inputs of "AND" and "OR" getes, and uses diode clamper in "NOT" gete, so that the common-emitter transistor that corries out inversion connot enter deep cut-off region. A diode and a resitance connect in series between the emitter and the ground for raising the potential of the emitter. Under same conditions, according to analogy experiment the circuit is 6 times faster than ECL circuit, and is 20 times faster than TTL circuit.
Application Number
申请号		 85108433 Application Date
申请日		 1985.11.18
Title 名称 High speed diode clamping "AND-OR-NOT" circuit
Publication Number
公开号		 1002986 Publication Date
公开日		 1986.09.03
Approval Pub. Date Granted Pub. Date
International Classification 分类号 H03K19/01
Applicant(s) Name
申请人		 Yang Guangyu
Address 地址
Inventor(s) Name 发明人
Attorney & Agent 代理人
More information 更  多  信  息


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