For the invention, each coupling element is composed of a C-MOS rejection gate and a C-MOS not both gate. The coupling element can be controlled by a special memory element for coupling point controlled by a decoder. One input end of the coupling element is connected with the signal input line while the other input end is connected with the output of the memory element (namely, the complementary output end). Two input ends of a C-MOS push-pull output circuit are connected with the output ends of the C-MOS rejection gate and the C-MOS not both gate, and the output of the push-pull output circuit forms the output of the coupling element. The push-pull output circuit looks just like the C-MOS rejection gate and the C-MOS not both gate and the power for the two source electrodes is supplied by two potential sources which meet the C-MOS logic levels. |