| Original document(35 pages) Authorized document(33 pages) 中文版 |
A kind of cache memory. It consists of two levels of pipeline shared by a group of sources, which includes two independently operating central processing units (CPUS). The cache memory includes a device used to distribute alternative time sections to two CPUS and to deviate their operations by one level of pipeline and to make one pipeline level read out the data buffer for one CPU, while the other pipeline level implements the catalog retrieve. Programs of each CPU are so designed that the time sections consumed are less than those obtained from the distribution. Accordingly, when the pipeline level is full of invoke processings of other sources, these processing units are capable of operating without conflict. |
Application Number
申请号 |
85107692 |
Application Date
申请日 |
1985.10.19 |
| Title 名称 |
Multiprocessor shared pipeline cache memory |
Publication Number
公开号 |
1010865 |
Publication Date
公开日 |
1987.05.06 |
| Approval Pub. Date |
|
Granted Pub. Date |
1993.06.09 |
| International Classification 分类号 |
G06F9/00,G06F9/38 |
Applicant(s) Name
申请人 |
Honeywell Bull Corp. |
| Address 地址 |
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| Inventor(s) Name 发明人 |
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| Attorney & Agent 代理人 |
LUAN BENSHENG |
| More information 更 多 信 息 |
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