The present circuit arrangement is principally directed to scrolling of a region or regions on a video display and includes a bit map memory, at least one address generation and control signal circuitry chip, one or more data signal path circuitry chips, timing circuitry and logic circuitry interconnecting the foregoing various sections of circuitry. The present arrangement functions to refresh, scroll and update during each horizontal scan, in response to a number of timing cycles. The foregoing arrangement permits the entire bit map memory to be rewritten during the period required for one vertical scan of the video display device which in turn enables the system to provide rapid smooth scrolling and continued sequential addressing of the memory. |