A digital circuit includes a full adder with a carry-bit latch and provided with a delay-and-subtract feedback network including at least one delay element and an inverter. The states of the latch and delay element may be preset to afford multiplicand correction and product truncation. The product is extracted at the adder output. The circuit also includes a control logic unit, for controlling series operation of the system. A shift register and exclusive-or gate are used in the multiplicand input path. Using these latter components the states of the latch and delay element are preset by a pre-run pass of the multiplicand through the adder and network. A binary-to-ternary converter is also disclosed comprising a pair of divide-by-three coefficient multiplier circuits configured in serial. |