| Original document(8 pages) 中文版 |
The present invention is a new demodulation technology of ASK signal and FSK signal. First-order loop as PLL filter constitutes new-type demodulation circuit, and the PLL detects the P-P value of input medium-freq signal to demodulate digital signal. The first-order PLL reduces the phase-locked threshold to 0.05 VPP, and makes the VCO operate in the fast tracking and locking state or oscillation stopping state. In the present invention, the PLL is equivalent to an amplitude-limiting amplifier with a dynamic range of more than 20 db, and its demodulated digital output has high amplitude of 3Vpp and strong noise immunity. |
Application Number
申请号 |
89102225 |
Application Date
申请日 |
1989.04.10 |
| Title 名称 |
Demodulation circuit |
Publication Number
公开号 |
1046423 |
Publication Date
公开日 |
1990.10.24 |
| Approval Pub. Date |
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Granted Pub. Date |
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| International Classification 分类号 |
H04L27/06,H04L27/14 |
Applicant(s) Name
申请人 |
Inst. No.63, Headquarters of the General Staff, CPLA |
| Address 地址 |
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| Inventor(s) Name 发明人 |
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| Attorney & Agent 代理人 |
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| More information 更 多 信 息 |
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