| Original document(86 pages) Authorized document(81 pages) 中文版 |
The present invention provides a semiconductor integrated circuit having area efficiency and repair efficiency improved by sharing a redundant memory macro among a plurality of SRAM macros. Each of the plurality of memory macros 1A1 and 1A2 includes a memory cell array 1A-3 connected to word lines WL1 to WL32 and bit lines and a redundant circuit that replaces a defective bit line of the memory cell array to a normal bit line and a redundant bit line BLA65 and outputs defect information to a redundant signal line RA. The redundant memory macro 2A includes a redundant memory cell array connected to redundant word lines and the redundant bit line, and a first word line connection circuit that connects a word line corresponding to a memory macro to be repaired and disconnects a word line corresponding to a normal memory macro from the redundant word line. |
Application Number
申请号 |
02151573 |
Application Date
申请日 |
2002.11.20 |
| Title 名称 |
Semiconductor integrated circuit comprising storage macro |
Publication Number
公开号 |
1423284 |
Publication Date
公开日 |
2003.06.11 |
| Approval Pub. Date |
2006.05.10 |
Granted Pub. Date |
2006.05.10 |
| International Classification 分类号 |
G11C11/34;G11C11/407 |
Applicant(s) Name
申请人 |
Matsushita Electric Industrial Co., Ltd. |
| Address 地址 |
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| Inventor(s) Name 发明人 |
Kurumata Mariaki;Akamatsu Hironori |
| Attorney & Agent 代理人 |
wu limeng wang zhongzhong |
| More information 更 多 信 息 |
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