This invention is a controlling chips set and the method of data transaction therein. The data buffering units of inner array of each controlling chip in the controlling chips set have fixed capacity and amount, and the sequence of sending confirming commands of reading and writing between chips makes a response according completely to the sequence in which the reading and writing commands are sent, making a controlling chip be able to hold completely the using status of the buffering units in inner array of another controlling chip. The method for excellence judgement sets a controlling right of some controlling chips for holding normal the bus between the chips, but another chip has higher priority right for bus, mating the specifications without waiting period of the bus between chips. |