During the three-dimensional integration of integrated circuits, a thinned semiconductor substrate (1) is arranged on a second semiconductor substrate and mechanically and electrically connected thereto. Continuous contact holes (24) are formed in the second semiconductor substrate (1) proceeding from a rear side (3) of the substrate to a first metal wiring plane on a front side of the substrate (12). In order to adjust the contact holes (24) on the structures arranged on the front side (2), a structure (4) is disposed on the front side (2) of the substrate (1) and is used as an adjusting mark (7) thereon (2). Said structure (4) is covered with a wear layer (15) and laid bare from the rear side (3) of the substrate (1) outwards so that the structure (4) can also be used as an adjusting mark (7) on the rear side. It is thus possible to avoid making an adjustment error between the structures arranged on the front side (2) and the rear side (3). |