A logarithm componding coded Turbo code decoder and its realizing method feature that the decoder comprises two channel decoders, two interleavers, two deinterleaves, demultiplex circuit, judgement devices and three memories. Imput/output ends of the said three memories are set up with circuit units of logarithm compressed and expanded coding to the input and outupt sequential signals of the corresponded memory respectively. The said three memories are used to store the received sequence by loyarithm compressed code during the said decoders processing the sequential signals, the outer information sequence after logarithm compressed coding and interleaving, output by the first decoder and outer information sequence via logarithm compressed coding and interleaving output by the second one. |