System with adjustable A/D converter clock phase

Original document(12 pages) Authorized document(12 pages) 中文版

An analog to digital converter with enhanced performance in the presence of clock noise interference are configured with sampling clock phase selection circuitry to enable operation of the converter at the optimum sampling time intervals with respect to the interfering noise. The selection circuitry includes apparatus for generating a plurality of sampling clock phases and a multiplexer coupled to the plurality of phases to select the optimum clock phase.

Application Number 申请号	00121703	Application Date 申请日	2000.06.04
Title 名称	System with adjustable A/D converter clock phase
Publication Number 公开号	1277492	Publication Date 公开日	2000.12.20
Approval Pub. Date	2005.02.02	Granted Pub. Date	2005.02.02
International Classification 分类号	H03M1/12;H04L5/00;H04N7/00
Applicant(s) Name 申请人	Thomson Licensing Corp.
Address 地址
Inventor(s) Name 发明人	Marc F. Lamraic;David L. Albie;John W. Jurk
Attorney & Agent 代理人	ma ying

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