Original document(12 pages) Authorized document(12 pages) 中文版
    An apparatus having a core processor and a memory system is disclosed. The core processor includes at least one data port. The memory system is connected in such a way as to provide substantially simultaneous data accesses through the data port. The memory system can be made user configurable to provide appropriate memory model.
Application Number
申请号		 01807691 Application Date
申请日		 2001.03.30
Title 名称 System having configurable cache/SRAM memory
Publication Number
公开号		 1429369 Publication Date
公开日		 2003.07.09
Approval Pub. Date 2005.09.21 Granted Pub. Date 2005.09.21
International Classification 分类号 G06F13/16
Applicant(s) Name
申请人		 Intel Corp.
Address 地址
Inventor(s) Name 发明人 H.S. Ramagopal;R. Kolagotla;D.B. Witt
Attorney & Agent 代理人 zhang zhengquan
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