An array of memory cells that includes a plurality of memory cells interconnected via a grid of M wordlines and M bitlines (224), wherein M = 2, 3, 4, 5,... and each of the M bitlines (224) is buried. The array further includes a plurality of contacts (228), wherein each of the plurality of contacts (228) is formed every N wordlines, N = 1, 2, 3,..., wherein each of the plurality of contacts (228) overlies a gate (229) of a different one of the plurality of memory cells. A strap (231) connects one of the buried bitlines (224) to a gate (229) that underlies one of the plurality of contacts (228) and a select transistor (232) is formed every P wordlines, wherein P is greater than N. |