An extracting transistor (10) - an FET - includes a conducting channel extending via a p-type InSb quantum well (22) between p-type InA1Sb layers (20, 24) of wider band-gap. One of the InA1Sb layers (24) incorporates an ultra-thin n-type delta -doping layer (28) of Si, which provides a dominant source of charge carriers for the quantum well (22). It bears n<+> source and drain electrodes (30a, 30b) and an insulated gate (30c). The other InA1Sb layer (20) adjoins a barrier layer (19) of still wider band-gap upon a substrate layer (14) and substrate (16) with electrode (18). Biasing one or both of the source and drain electrodes (30a, 30b) positive relative to the substrate electrode (18) produces minority carrier extraction in the quantum well (22) reducing its intrinsic contribution to conductivity, taking it into an extrinsic saturated regime and reducing leakage current. |