| Original document(34 pages) Authorized document(34 pages) 中文版 |
A conditional select adder having a carry generating unit which generates a carry of two n-bit input data units X0-Xn-1, and Y0-Yn-1, and a sum generating unit which generates the sum of the input data, is provided. The carry generating unit comprises a first input unit which receives predetermined data based on the input data Xi and Yi; a second input unit which receives the initial carry; and a selection unit which receives the result of performing an XOR operation on the input data Xi and Yi, in which according to the XOR result, either predetermined data based on the input data Xi and Yi input to the first input unit, or the initial carry input to the second input unit is selected and output as a carry. The sum generating unit calculates a sum using the carry generated by the carry generating unit. Advantages include reducing power consumption, chip area, logic count, and delay time. |
Application Number
申请号 |
02140712 |
Application Date
申请日 |
2002.07.12 |
| Title 名称 |
XOR carrying generator and condition-selecting adder and method with the generator |
Publication Number
公开号 |
1432907 |
Publication Date
公开日 |
2003.07.30 |
| Approval Pub. Date |
2005.07.06 |
Granted Pub. Date |
2005.07.06 |
| International Classification 分类号 |
G06F7/00 |
Applicant(s) Name
申请人 |
Samsung Electronics Co., Ltd. |
| Address 地址 |
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| Inventor(s) Name 发明人 |
Cho Gi-Sun |
| Attorney & Agent 代理人 |
ma ying shao eli |
| More information 更 多 信 息 |
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