In the present invention, multiple microprocessor, system has m microprocessors and a chipset connected to the microprocessors via bus. The chipset includes a memory unit and a comparator connected electrically to the memory, and m pieces of work load information for the m microprocessors are stored in the memory with the idle microprocessor corresponding to the highest work load grade .The chipset responds and interruption service request to generate one comparison signal, so that the comparator compares the m pieces of work load information and the microprocessor being not in idle state but in lowest work load grade with process some interruption service request prior. |