Original document(25 pages) Authorized document(27 pages) 中文版
    A mechanism is provided for recovering from a failing load check instruction in a processor that implements advanced load instructions. An advanced load address table (ALAT) tracks status information for the advanced load instruction. The status information is read when an associated load check operation is processed, and an exception is triggered if the status information indicates data returned by the advanced load operation was modified by a subsequent store operation. The load check instruction is converted to a load operation, instructions are flushed from the processor's instruction execution pipeline, and the pipeline is resteered to the first instruction that follows the load check instruction.
Application Number
申请号
00818993 Application Date
申请日
2000.11.20
Title 名称 Mechanism for handling failing load check instructions
Publication Number
公开号
1434939 Publication Date
公开日
2003.08.06
Approval Pub. Date 2006.03.29 Granted Pub. Date 2006.03.29
International Classification 分类号 G06F9/38
Applicant(s) Name
申请人
Intel Corp.
Address 地址
Inventor(s) Name 发明人 J.K. Arora
Attorney & Agent 代理人 wu limeng wang yong
More information 更  多  信  息


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