A process for preparing a MOS transistor in order to prevent the grid depletion of MOS transistor in NROM and increase the grid drive power includes providing a semiconductor chip having the defined memory array area and peripheral circuit area on its surface, generating a grid consisting of a Si-O layer, a non-crystal Si layer and a silicon germanium layer on the surface of said peripheral circuit area, generating the side wall, source and drain around the grid, generating a Ni layer on the top of grid, and fast annealing at 400-500 deg.C for generating a Ni-Si layer on silicon germanium layer. |