A process for preparing shallow-junction MOS transistor in NROM includes providing a semiconductor chip having the defined memory array area and peripheral circuit area on its surface, generating a gate consisting of Si-O layer, and silicon germanium layer on the surface of said peripheral circuit area, generating side wall, source and drain around the gate, generating a Ni layer on the surface of source and drain, and annealing at 400-500 deg.C to generate a Ni-Si layer on the surface of source and drain and the shallow junction of source and drain. |