| Original document(17 pages) Authorized document(17 pages) 中文版 |
A switching power supply circuit is protected from degradation and breakage of a MOS transistor when the inductive load is short-circuited or overloaded. To do this, the magnitude of the load current flowing through the MOS transistor is detected by a differential amplifier as a voltage drop due to the on resistance of the MOS transistor, a first latch circuit is set by the detection output of the differential amplifier generated when the voltage drop exceeds a predetermined value, and the first latch circuit is reset by the output of a control signal generating circuit controlling the MOS transistor. Current supplies from two constant current sources are switched between in accordance with the output of the first latch circuit to charge and discharge a capacitor for timer time setting. Then, the charging voltage of the capacitor is detected by a comparator, and a second latch circuit is set by the output of the comparator generated when the charging voltage exceeds a predetermined value. Then, the supply of a control signal from the control signal generating circuit to the MOS transistor is inhibited by the output of the second latch circuit. |
Application Number
申请号 |
03104209 |
Application Date
申请日 |
2003.01.29 |
| Title 名称 |
Switch Power supply circuit |
Publication Number
公开号 |
1435942 |
Publication Date
公开日 |
2003.08.13 |
| Approval Pub. Date |
2006.09.27 |
Granted Pub. Date |
2006.09.27 |
| International Classification 分类号 |
H02M1/00;H02M3/155 |
Applicant(s) Name
申请人 |
Matsushita Electric Industric Co., Ltd. |
| Address 地址 |
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| Inventor(s) Name 发明人 |
Kimura Ichito |
| Attorney & Agent 代理人 |
wang yue zhang zhicheng |
| More information 更 多 信 息 |
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