Original document(32 pages) Authorized document(32 pages) 中文版
    The present invention is directed to simplify a circuit for fixing an output logic of a logic gate while suppressing a subthreshold current. A logic circuit has an n-channel type first transistor capable of interrupting power supply to a logic gate in accordance with an input control signal, and a p-channel type second transistor capable of fixing an output node of the logic gate to a high level interlockingly with the power supply interrupting operation by the first transistor, and a threshold of the first transistor is set to be higher than that of a transistor as a component of the logic gate. Means for interrupting the power supply to the logic gate is realized by the first transistor, and means for fixing an output node of the logic gate to the high level is realized by the second transistor, thereby simplifying the circuit for fixing the output logic of the logic gate while suppressing a subthreshold current.
Application Number
申请号
03102313 Application Date
申请日
2003.01.30
Title 名称 Logical circuit and semiconductor device
Publication Number
公开号
1435947 Publication Date
公开日
2003.08.13
Approval Pub. Date 2007.01.17 Granted Pub. Date 2007.01.17
International Classification 分类号 H03K19/094;H03K19/003;H01L27/02
Applicant(s) Name
申请人
Toshiba K.K.
Address 地址
Inventor(s) Name 发明人 Saifuji Yoshikazu;Osada Kenichi
Attorney & Agent 代理人 wang yonggang
More information 更  多  信  息


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