An architecture according to the present invention performs arithmetic operations on a composite field over dual basis. The ground field arithmetic is performed under dual basis. Therefore, the proposed architectures has the advantages of both composite field and dual basis processing, area efficiency and timing efficiency. Moreover, if the ground field GF(2<n>) arithmetic is implemented by bit-serial operation, the overall throughput of the composite field GF((2<n>)<k>) arithmetic will be twice than the one implemented in the finite field GF(2<m>)m=nk). |