A semiconductor device having a vertical MOSFET structure well balanced between high withstand voltage and low ON resistance is provided as having an n+-type semiconductor substrate 101 as a first-conductivity-type semiconductor substrate, an n-type drift region 102 as a first-conductivity-type drift region formed on the surface of an n+-type semiconductor substrate 101, a p-type base region 108 as a second-conductivity-type base region formed in the surficial portion of the n-type drift region 102, a p-type buried region 4 as a second-conductivity-type buried region provided in the n-type drift region 102, as being spaced from the p-type base region 108 towards the n+-type semiconductor substrate 101, and a gate electrode 107 A provided so as to penetrate the p-type base region 108 and further to reach a predetermined depth in the n-type drift region 102. |