| Original document(86 pages) 中文版 |
The recording apparatus adds EDC to user data and transfers the EDC-added data to the scrambler in a sequence different from the coding direction Q. Though the processing data is added at an end in the direction Q, it is inserted at middle in the different sequence. Therefore, in order to transfer the EDC-added data in the different sequence, the EDC generator calculates an EDC intermediate value from an expected value of a latter part of an even number sector. Then, the EDC generator receives the user data in the different sequence and calculates EDC from expected values of the first half of the even number sector and an odd number sector and the EDC intermediate value. The expected value is an error detecting value of code string that has the same number of bits as the EDC-added data and a corresponding bit in the sequence of the direction Q is 1 and other bits are 0. |
Application Number
申请号 |
200610108459 |
Application Date
申请日 |
2006.08.04 |
| Title 名称 |
Error detecting code calculation circuit, error detecting code calculation method, and recording apparatus |
Publication Number
公开号 |
1909100 |
Publication Date
公开日 |
2007.02.07 |
| Approval Pub. Date |
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Granted Pub. Date |
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| International Classification 分类号 |
G11B20/10;G11B20/18;H03M13/00;G06F11/08 |
Applicant(s) Name
申请人 |
NEC Electronics Corp. |
| Address 地址 |
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| Inventor(s) Name 发明人 |
Ariyama Takeo |
| Attorney & Agent 代理人 |
guan zhaohui lu jinhua |
| More information 更 多 信 息 |
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