| Original document(67 pages) 中文版 |
Disclosed herein is a charge trap-type 3-level non-volatile semiconductor memory device and method of driving the same. The charge trap-type 3-level non-volatile semiconductor memory device includes a memory array including a plurality of memory elements, each capable of storing data in at least two charge trap regions depending on the direction of current flow, and a page buffer driven to map three data bits to threshold voltage groups of the two charge trap regions. The charge trap-type non-volatile semiconductor memory device has charge trap regions each storing 1.5 bits of data. That is, a single memory element has charge trap regions for storing 3 bits of data, thereby improving device integration while maintaining a high operating speed during programming and reading operations. |
Application Number
申请号 |
200610008628 |
Application Date
申请日 |
2006.02.20 |
| Title 名称 |
Charge trap-type 3-level non-volatile semiconductor memory device and method of driving the same |
Publication Number
公开号 |
1909111 |
Publication Date
公开日 |
2007.02.07 |
| Approval Pub. Date |
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Granted Pub. Date |
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| International Classification 分类号 |
G11C16/00;G11C16/06;G11C16/10 |
Applicant(s) Name
申请人 |
Samsung Electronics Co., Ltd. |
| Address 地址 |
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| Inventor(s) Name 发明人 |
Park Ki-tae;Choi Jung-dal |
| Attorney & Agent 代理人 |
huang xiaolin wang zhisen |
| More information 更 多 信 息 |
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