| Original document(24 pages) 中文版 |
A connector layout for arranging a plurality of parallel electrical connectors between two electronic devices. In one device, each connector has a strip connected to a bump pad. The bump pad is superimposed on and electrically connected to a bump pad on the other device. Each strip has a certain required strip width and each bump pad has a certain required pad width. The connectors are grouped into a group of three or more. Within each group, a strip is connected to a bump pad along one side edge thereof, and the bump pads are offset in two directions such that after the bump pads are superimposed, the pattern of the connected connectors in each group of connectors resembles a plurality of zigzag paths offset to maintain a constant gap between two strips. As such, the gap between two connectors can be minimized. |
Application Number
申请号 |
200610108168 |
Application Date
申请日 |
2006.07.31 |
| Title 名称 |
Method for improving electron circuit layout efficiency, electronic connector and electronic panel |
Publication Number
公开号 |
1913117 |
Publication Date
公开日 |
2007.02.14 |
| Approval Pub. Date |
|
Granted Pub. Date |
|
| International Classification 分类号 |
H01L21/60;H01L25/00;H01L23/488;G02F1/133 |
Applicant(s) Name
申请人 |
AU Optronics Corp. |
| Address 地址 |
|
| Inventor(s) Name 发明人 |
Peng Wen-hui;Chen Chien-chung;Chen Yu-ching |
| Attorney & Agent 代理人 |
wei xiaogang li xiaoshu |
| More information 更 多 信 息 |
|
|
|