| Original document(18 pages) 中文版 |
Methods of forming dual-damascene metal wiring patterns include forming a first metal wiring pattern (e.g., copper wiring pattern) on an integrated circuit substrate and forming an etch-stop layer on the first metal wiring pattern. These steps are followed by the steps of forming an electrically insulating layer on the etch-stop layer and forming an inter-metal dielectric layer on the electrically insulating layer. The inter-metal dielectric layer and the electrically insulating layer are selectively etched in sequence to define an opening therein that exposes a first portion of the etch-stop layer. This opening may include a trench and a via hole extending downward from a bottom of the trench. A first barrier metal layer is formed on a sidewall of the opening and directly on the first portion of the etch-stop layer. A portion of the first barrier metal layer is selectively removed from the first portion of the etch-stop layer. The first portion of the etch-stop layer is then selectively etched for a sufficient duration to expose a portion of the first metal wiring pattern. A second metal wiring pattern is formed in the opening in order to complete a dual-damascene structure. |
Application Number
申请号 |
200610121251 |
Application Date
申请日 |
2006.08.07 |
| Title 名称 |
Methods of forming dual-damascene metal wiring patterns for integrated circuit devices and wiring patterns formed thereby |
Publication Number
公开号 |
1913128 |
Publication Date
公开日 |
2007.02.14 |
| Approval Pub. Date |
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Granted Pub. Date |
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| International Classification 分类号 |
H01L21/768;H01L23/522 |
Applicant(s) Name
申请人 |
Samsung Electronics Co., Ltd. |
| Address 地址 |
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| Inventor(s) Name 发明人 |
Lee Boung-ju;Shin Heon-jong;Kang Hee-sung |
| Attorney & Agent 代理人 |
tao fengbei |
| More information 更 多 信 息 |
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