| Original document(39 pages) 中文版 |
In a method for manufacturing a semiconductor device, an oxide layer, a first polysilicon layer, and a second polysilicon layer are sequentially provided on a substrate. A first hard mask pattern is provided on the second polysilicon layer. The oxide layer, the first polysilicon layer, and the second polysilicon layer are patterned using the first hard mask pattern as a mask to form a lower gate structure including an oxide pattern, a first polysilicon pattern, and a second polysilicon pattern. The lower gate structure is etched to provide an oxidation layer on sidewalls of the lower gate structure. An insulating layer is provided on the lower gate structure including the oxidation layer. The first hard mask pattern is removed to form a first opening in the insulating layer, the first opening exposing the second polysilicon pattern. A metal pattern is formed in the first opening on the second polysilicon pattern, the second polysilicon pattern having the oxidation layer on sidewalls thereof. |
Application Number
申请号 |
200610106896 |
Application Date
申请日 |
2006.08.09 |
| Title 名称 |
Nonvolatile semiconductor integrated circuit devices and fabrication methods thereof |
Publication Number
公开号 |
1913132 |
Publication Date
公开日 |
2007.02.14 |
| Approval Pub. Date |
|
Granted Pub. Date |
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| International Classification 分类号 |
H01L21/8247;H01L21/336;H01L21/28;H01L27/115;H01L29/788;H01L29/40 |
Applicant(s) Name
申请人 |
Samsung Electronics Co., Ltd. |
| Address 地址 |
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| Inventor(s) Name 发明人 |
Kim Tae-kyung;Choi Jeong-hyuk |
| Attorney & Agent 代理人 |
lin yuqing xie lina |
| More information 更 多 信 息 |
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