This invention relates to a memory element and its manufacturing method, in which, said element includes a base, a first insulation layer, a charge storage layer, a second insulation layer, a gate electrode layer and a source/drain region, in which, the forbidden gap of the base is greater than that of silicon, the first insulation layer is set on the base, the charge storage layer is set on the first insulation layer, the second insulation layer is set on the charge storage layer, the gate electrode layer is set on the second insulation layer, in which, the gate electrode layer, the second insulation layer, the charge storage layer and the first insulation layer form a stack structure, the source/drain region is set in the base at both sides of the stack structure. |