Original document(11 pages)  中文版
    A processor includes a plurality of logical processors, and an instruction set, the instruction set including of one or more instructions which when executed by a first logical processor, cause the first logical processor to make a processor execution resource previously reserved for the first processor available to a second processor in the plurality of processors in response to the first logical processor being scheduled to enter an idle state.
Application Number
申请号		 200580003909 Application Date
申请日		 2005.01.14
Title 名称 Sharing idled processor execution resources
Publication Number
公开号		 1914593 Publication Date
公开日		 2007.02.14
Approval Pub. Date Granted Pub. Date
International Classification 分类号 G06F9/38;G06F9/46
Applicant(s) Name
申请人		 Intel Corp.
Address 地址
Inventor(s) Name 发明人 Yamada Koichi;Kay Allen
Attorney & Agent 代理人 yan shen
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