The present invention is directed to obtain further low power dissipation in the structure in which each pixel has a memory circuit. The pixel circuit(20)comprises TFT(122, 124, 126, 128), a memory circuit(30)and a liquid crystal cell(150). TFT(122, 124)or(126, 128)is arranged between the bit line(215)(the complementary bit line(216))and the memory circuit(30)at the time of concurrent selection of an X selection line(211)and a Y selection line(311)corresponding to the pixel block to which the plurality of the transistors belong. The memory circuit(30)keeps the data bit supplied by the corresponding bit line(215)when the TFT(122, 124)or(126, 128)are both switched into conduction. The liquid crystal cell(150)switches into any display status of turn-on or turn-off. |