Original document(27 pages)  中文版
    This invention relates to H.264 integral number acieration device, which comprises the following parts: data memory connected to data bus; vector computation register set to receive original data as vector data; summing register set data with each register Ri composed of four work register RiO, Ri1, Ri2 and Ri3; eight path vector data connection to run data operation; sum register set to store Ri acieration middle data; controller to operate data and designing selection signals.
Application Number
申请号		 200510061704 Application Date
申请日		 2005.11.25
Title 名称 H.264 integer transformation accelerator
Publication Number
公开号		 1929603 Publication Date
公开日		 2007.03.14
Approval Pub. Date Granted Pub. Date
International Classification 分类号 H04N7/24;G06F15/80
Applicant(s) Name
申请人		 Zhejiang University
Address 地址
Inventor(s) Name 发明人
Attorney & Agent 代理人 wangbing huangmei juan
More information 更  多  信  息


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