| Original document(61 pages) 中文版 |
To prevent a non-reaction polysilicon region or a region where the composition of a silicide is locally different from being generated in a gate electrode due to pattern dependency such as a gate length or a gate region when integrating the gate electrode of a transistor into a full silicide. A semiconductor device is provided with a first N type MIS transistor 51 successively formed in a first region A of a semiconductor substrate 100, and having a first gate insulating film 104A and a first gate electrode 115A integrated into the full silicide and a second N type MIS transistor 52 successively formed in a second region B of the semiconductor substrate 100, and having a second gate insulating film 104B and a second gate electrode 115B integrated into the full silicide. The gate length of the second gate electrode 115B is made larger than the gate length of the first gate electrode 115A, and the thickness of the central part of the gate length direction in the second gate electrode 115B is made smaller than that of the first gate electrode 115A. |
Application Number
申请号 |
200610093208 |
Application Date
申请日 |
2006.06.22 |
| Title 名称 |
Semiconductor device and method for fabricating the same |
Publication Number
公开号 |
1933158 |
Publication Date
公开日 |
2007.03.21 |
| Approval Pub. Date |
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Granted Pub. Date |
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| International Classification 分类号 |
H01L27/088;H01L27/092;H01L21/8234;H01L21/8238 |
Applicant(s) Name
申请人 |
Matsushita Electric Ind Co., Ltd. |
| Address 地址 |
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| Inventor(s) Name 发明人 |
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| Attorney & Agent 代理人 |
wanghui min |
| More information 更 多 信 息 |
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