There provided are a layout configuration in which fluctuation in pixel sensitivity characteristics is reduced and a solid-state image pickup device which attains high yield and high sensitivity. Respective sections included in pixels 2 a and 2 b, such as light receiving regions 20 a and 20 b of PDs 3 a and 3 ba, transfer gate electrodes 4 a and 4 b, and FD 5 , have outer shapes comprising lines extending in row directions and lines extending in column directions. The light receiving regions 20 a and 20 b, the transfer gate electrodes 4 a and 4 ba, and FD 5 which the pixel pair includes are disposed in an axisymmetrical manner with respect to a straight line extending between the 2 pixels of the pixel pair. And FD 5 and source regions and drain regions of a reset transistor 6 and an amplifier transistor 12 are disposed in a straight line extending in a column direction. |