This invention relates to a high voltage MOS transistor including a base, a trap region, a grating insulation layer, a grid, two drift regions, a channel region, a source/drain region and an isolation structure, in which, the trap region is stationed in the base, the grating insulation layer is on the base, the grid is set on the grating insulation layer, the two drift regions are configured in the trap at both sides of the grid, the width of the grid is smaller than or equal to that of the drift region, the channel region is set between the two drift regions and the width of which is greater than that of the two drift regions, the source/drain region is matched in the two drift regions separately, the isolation structure is placed between the source/drain region and the channel region and the two drift regions surround the source/drain region and the isolation structure. |