Original document(44 pages)  中文版
    A low voltage of the order of or one to three volts instead of an intermediate VPASS voltage (e.g. of the order of five to ten volts) is applied to word line zero (WLO) immediately adjacent to the source (SGS) or drain side select gate of a NAND flash device (100) to reduce or prevent the shifting of threshold voltage of the memory cells coupled to word line zero during the programming cycles of the different cells of the NAND strings. This may be implemented in any one of a variety of different self boosting schemes including erased areas self boosting and local self boosting schemes.
Application Number
申请号		 200580008885 Application Date
申请日		 2005.01.20
Title 名称 Self-boosting system for flash memory cells
Publication Number
公开号		 1934653 Publication Date
公开日		 2007.03.21
Approval Pub. Date Granted Pub. Date
International Classification 分类号 G11C16/00;G11C16/04;G11C11/56
Applicant(s) Name
申请人		 Sandisk Corp.
Address 地址
Inventor(s) Name 发明人
Attorney & Agent 代理人 liuguo wei
More information 更  多  信  息


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