A test device includes: a pattern generator for generating an address signal, a data signal, and expectation signal for supply to a plurality of memories under test; a plurality of logic comparators for generating fail data when the output signal outputted from the memories under test do not coincide with the expectation signal; a plurality of fail memories for storing fail data generated by the logic comparators; a plurality of memory controllers for generating defective address information indicating a defective address of the memory under test according to the fail data stored in the fail memories; a plurality of universal buffer memories for storing the defective address information generated by the memory controllers; and a plurality of defect information write units for writing defect information in parallel into the defect address indicated by the defective address information stored in the universal buffer memories of the memories under test. |