The present invention relates to a method for detecting delay faults in a semiconductor memory. In an example embodiment (100), address bits and data bits are generated (110) according to a test pattern suitable for testing the semiconductor memory. The address bits and the data bits are validated (120) and then provided to input ports (130) of the semiconductor memory. Memory operation (140, 150, 160, 170) is then started such that a time interval between the provision of the address bits and the data bits and the start of the memory operation is approximately equal to an operating clock cycle of the semiconductor memory. Such timing ensures that both the address decoder and the read/write circuitry are stressed in time appropriately, enabling detection of small delay faults. |